As technology nodes decrease, the density of features on a substrate increases. In some instances the density of features of a layout design is higher than resolution capabilities of a single mask lithography process. When more than one mask is utilized to transfer the layout design to a wafer, a layout engineer must determine which features to place on each mask. Due to variations during manufacturing processes, features formed using different masks occasionally experience a mismatch, i.e., shapes of features transferred to the wafer by different masks are slightly different even when the desired shapes are the same. The resulting mismatch adversely impacts the performance of circuits formed by the features. In some instances, the mask related mismatches cause the circuits to fail quality control tests resulting in a lower production yield.
To help reduce the number of mask related mismatches, a circuit designer includes instructions regarding which features to form using the same mask. The layout engineer receives the instructions and designs the mask accordingly. However, confirming the accuracy of the layout design in comparison with the circuit design is performed manually and in some instances errors are overlooked.